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PIC18F/LF1XK50

DS41350E-page 102

Preliminary

2010 Microchip Technology Inc.

10.1

Timer0 Operation

Timer0 can operate as either a timer or a counter; the

mode is selected with the T0CS bit of the T0CON

increments on every clock by default unless a different

prescaler

value

selected

(see

Section 10.3

“Prescaler”). Timer0 incrementing is inhibited for two

instruction cycles following a TMR0 register write. The

user can work around this by adjusting the value written

to the TMR0 register to compensate for the anticipated

missing increments.

The Counter mode is selected by setting the T0CS bit

(= 1). In this mode, Timer0 increments either on every

rising or falling edge of the T0CKI pin. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit, T0SE of the T0CON register; clearing this bit

selects the rising edge. Restrictions on the external

clock input are discussed below.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements (see

Table 27-6) to ensure that the external clock can be

synchronized with the internal phase clock (TOSC).

There is a delay between synchronization and the

onset of incrementing the timer/counter.

10.2

Timer0 Reads and Writes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode; it is actually a buffered version of the real high

byte of Timer0 which is neither directly readable nor

writable (refer to Figure 10-2). TMR0H is updated with

the contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without the need to verify that the read of the

high and low byte were valid. Invalid reads could

otherwise occur due to a rollover between successive

reads of the high and low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. Writing

to TMR0H does not directly affect Timer0. Instead, the

high byte of Timer0 is updated with the contents of

TMR0H when a write occurs to TMR0L. This allows all

16 bits of Timer0 to be updated at once.

FIGURE 10-1:

TIMER0 BLOCK DIAGRAM (8-BIT MODE)

Note:

Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks

TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

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